Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Integrated circuits, such as PLDs, may include components that need a reset capability. In particular, an integrated circuit component may have either an asynchronous or a synchronous reset capability. In some situations a design engineer needs a component with an asynchronous reset, and in other situations needs a component with a synchronous reset. However, the component available to the designer may have a synchronous reset in a situation where a designer needs an asynchronous reset, or may have an asynchronous reset in a situation where a designer needs a synchronous reset.
Depending on design requirements, a design engineer may also need to enable and disable a clock signal. When the engineer needs both reset and clock enable/disable capabilities, the engineer often needs one of the clock and reset signals take priority over the other. For example, the engineer may not want an integrated circuit component to reset when the clock signal is disabled, or may want to reset the component when the clock signal to the integrated circuit is disabled. In the case of a typical circuit component that has both reset capability and clock enable capability, one of the reset and clock enable will inherently have priority over the other. However, the component available to the designer may give the reset priority over the clock enable in a situation where the engineer needs the clock enable to have priority over the reset, or may give the clock enable priority over the reset where the engineer needs the reset to have priority over the clock enable. Consequently, although existing components in integrated circuits have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.